The development of reprogrammable radio transceivers, which can be operated in accordance with multiple standards, is an important goal being pursued by the wireless communications industry. Reprogrammable radio transceivers are expected to provide a relatively inexpensive way to produce flexible handsets that can be reconfigured for use in any wireless network without having to change the hardware platforms involved. The ability to achieve this development goal would enable a successful company to drive up its handset production volumes, and drive down its production costs. However, the industry also recognizes that the hardware that accompanies such multi-standard transceivers will have to be capable of accommodating the broad level of programmability required, but changes to the existing software, hardware, and the associated costs will have to be minimized.
In this regard, a significant problem that exists in the design of reprogrammable radio transceivers is that the processes currently used to configure Digital Signal Processor- (DSP-) related digital hardware are extremely time- and resource-consuming, because of the relatively large number of configuration registers involved. For example, the number of registers involved in programming a relatively complicated DSP component (e.g., digital filter pipeline) can be on the order of 100s of registers. Also, the time required to individually program all the registers in a digital filter pipeline (e.g., using typical serial interfaces) can take up to 100 msecs for each 100 registers in the set. Furthermore, the use of multiple register sets to hold N configurations will require N times the number of registers, which will result in substantially longer device boot-up times and more die area.
Unfortunately, the typical software timing budgets currently available for existing analog, single standard transceiver front-end solutions provide only enough time to configure between 3 to 10 DSP-related registers. However, the exceptionally large number (e.g., 100s) of registers that are expected to be used in future reprogrammable radio transceivers will require new design solutions in order to limit power consumption, minimize the impact on existing Radio Frequency (RF) drivers, reduce the number of hardware resources to be used, and create a suitable balance between transceiver programmability and design flexibility.